1. Field of the Invention
The present invention relates generally to logic circuits and particularly to such logic circuits where two different circuit branches are connected between input and output to calculate a result and an inverted result in dependency on one or several inputs.
2. Description of Prior Art
Circuits of this type are used, for example, in circuits with a dual rail encoding or in circuits of the NCL (Null Convention Logic® (registered trademark)) of the company Theseus or in different circuits.
FIG. 4 generally shows the structure of such logic circuits based on an example of a logic device, which maps two input operands, A, B to one result operand C and outputs the result C as well as the inverted result {overscore (C)}. As can be seen from FIG. 4, the logic device, which is generally indicated with 300, consists of two inputs 302 and 304 for the input operands A and B, respectively, on the input side, of two outputs 306 and 308 for the result C and the inverted result {overscore (C)}, respectively, on the output side and in-between of two logic assemblies 310 and 312, each of which is coupled to both inputs 302 and 304, and the logic assembly 310 is coupled to the output 306, and the logic assembly 312 to the output 308.
The logic assemblies 310 and 312 are equalized to perform together a certain logic function with regard to the input operands A and B, such as an AND, OR or XOR function, or another complicated function. Accordingly, the logic assembly 310 is provided for calculating the result C from the input operands A and B, while the logic assembly 312 is provided to calculate the inverted result {overscore (C)} from the input operands A and B. Depending on the type of logic function and the used gates within the logic assemblies 310 and 312, the selection of which, in turn, depends, for example, on the production technique used for the integration of the logic circuit, the logic assemblies 310 and 312 require different durations and different powers for the calculation of the result C and the inverted result {overscore (C)}, respectively. In other words, the logic assemblies 310 and 312 can have different run times and different power consumptions.
It is a disadvantage of the logic device described with reference to FIG. 4 that when using such logic devices in cryptographical circuits, such as chip cards or SIM cards, different run times and power consumption are caused, depending on the data to be encrypted within a logic device according to FIG. 4, which, in turn, present a potential for possible attacks, for example to draw conclusions about the used cryptography algorithm, the cryptographic key and other secret data. Attacks, which are suited for this, are referred to as hardware attacks, such as DPA (differential power analysis) and timing attacks. In the case that, for example, the logic device of FIG. 4 operates clocked within a synchronous logic, the course of the power consumption of the circuit changes within one clock, since, depending on the input data, more logic branches with that logic assembly switch to a logical high state, such as 5 V, as the result, and, in the case of a CMOS implementation, consume power thereby, which have a higher or lower power consumption and a longer or shorter run time, respectively, compared to the respectively different logic branches. In the case of the logic device of FIG. 4, for example, the power consumption as well as the time course of this power consumption differ for different input operands A and B depending on which of the two logic branches, namely the one into which the logic assembly 310 is switched or the one into which the logic assembly 312 is switched, outputs a logical high state as result and inverted result, respectively.
Even more serious is the effect of the different run times of power consumption of the different circuit branches of the different logic devices in the case of using them in asynchronous circuits as self-clocked logic devices. Depending on the data to be processed and to be encrypted, respectively, the different power consumptions and run times, which occur depending on which of the power branches “switches”, add to a different total power consumption and total calculating duration per encryption or sub-operation of a cryptographical algorithm.